1. Field of Invention
The present invention relates to a package and a method for manufacturing thereof. More particularly, the present invention relates to a chip package with only one side for bonding process.
2. Description of Related Art
With electronic products in daily life becoming smaller and thinner, semiconductor chips disposed in those electronic products have to be miniaturized accordingly. On the other hand, functions of the semiconductor chips are still increasing when they are miniaturized. In order to improve reliabilities of the semiconductor chips, most semiconductor chips are fabricated into chip packages. Bonding wires are bonded to input/output (I/O) conducting pads of the chip packages, and the chip packages are integrated with a printed circuit board (PCB) to perform predetermined functions of the semiconductor chips. FIG. 1A is a top view of the chip package of prior art, and FIG. 1B is a cross-sectional view of AA′ line in FIG. 1A. As illustrated in FIG. 1A and FIG. 1B, the semiconductor chip package 1 includes a semiconductor chip 2 and a plurality of bonding wires 4. The semiconductor chip 2 has a plurality of I/O conducting pads 2a and a plurality of holes 2b (labeled in dot lines). As shown in FIG. 1B, when the semiconductor chip 2 is fabricated into the semiconductor chip package 1, etching processes are performed from an upper surface US to a lower surface DS of the semiconductor chip 2 to yield the plurality of holes 2b. Therefore, the plurality of I/O conducting pads 2a is exposed. The bonding wires 4 are respectively bonded to the I/O conducting pads 2a such that a PCB could be electrically connected to the semiconductor chip 2 through the bonding wires 4. To perform the operation of bonding the bonding wires 4 to the I/O conducting pads 2a, the holes 2b formed by the etching processes are required to be deep and board enough so as to expose the I/O conducting pads 2a and provide space for a bonding-wire carrier to enter therein. As illustrated in FIG. 1B, a distance a must exist between sidewalls of the hole 2b and the connection of bonding wire 4 and the I/O conducting pads 2a. In other words, large wire-bonding area is required. Therefore, space for interconnections in the semiconductor chip 2 with a given area is accordingly limited by the distance a. As aforementioned, functions of the semiconductor chips are still required to be increased even when they are miniaturized. Therefore, in the semiconductor chip 2 with a given area, space for interconnections should be increased to provide more flexibility on layout design of interconnections such that functions of the semiconductor chip 2 could be further enhanced. However, known chip packages and manufacturing thereof that require large wire-bonding area and limit the space for interconnections in the semiconductor chip.